Digital non-volatile memories are well known. For example, FIG. 1 depicts four-gate split-gate flash memory cell 100 comprising source region 101, drain region 102 (coupled to bit line 24), floating gate 103 over a first portion of channel region 104, word line terminal 105 (typically coupled to a word line) over a second portion of channel region 104, substrate 108, control gate 106 (typically coupled to a control gate line) over floating gate 103, and erase gate 107 (typically coupled to an erase gate line) over the source region 101. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes). Here, all gates are non-floating gates except floating gate 103, meaning that they are electrically connected or connectable to a voltage source. Programming of memory cell 100 occurs by causing heated electrons to be injected from channel region 104 into floating gate 103. Erasing of memory cell 100 occurs by causing electrons to tunnel from floating gate 103 to erase gate 107.
Table No. 1 depicts typical voltage ranges that can be applied to the terminals of memory cell 100 for performing read, erase, and program operations:
TABLE NO. 1Operation of Flash Memory Cell 100 of FIG. 1WLBLCGEGSLRead1.0-2 V0.6-2 V0-2.6 V0-2.6 V0 VErase−0.5 V/0 V0 V0 V/−8 V8-12 V0 VProgram1 V1 μA8-11 V4.5-9 V4.5-5 V
FIG. 2A shows prior art flash memory system 200, which comprises an array of cells 100 arranged in rows and columns. Here, only two rows and seven columns are shown, but it is to be understood that the array can comprise any number of rows and any number of columns. Cells 100 in this example are of the type shown in FIG. 1, wherein the erase gate is shared or merged among two adjacent rows.
In the top row of cells shown in FIG. 2A, word line 201 connects to each word line terminal 105 of each cell 100 in that row, control gate line 202 connects to each control gate terminal 106 of each cell 100 in that row, and erase gate line 203 connects to each shared erase gate terminal 107 of each cell 100 in that row.
In the second row of cells shown in FIG. 2A, word line 205 connects to each word line terminal 105 of each cell 100 in that row, control gate line 204 connects to each control gate terminal 106 of each cell 100 in that row, and erase gate line 203 connects to each shared erase gate terminal 107 of each cell 100 in that row. Notably, erase gate line 203 connects to erase gate terminal 107 of each cell 100 shared among the top row and the second row.
With reference to FIG. 2B, the close proximity of word lines, control gate lines, and floating gates create parasitic effects. Specifically, parasitic capacitance will exist between adjacent word lines and control gate lines, such as between word line 201 and control gate line 202 and between word line 205 and control gate line 204, and parasitic capacitance also will exist between word line 201 and the floating gates in each cell 100 in the top row and between word line 205 and the floating gates in each cell 100 in the second row.
The parasitic capacitance can be modeled with: (1) parasitic capacitor 210 located within each cell 100, with one terminal connected to a word line and one terminal connected to a control gate line, and (2) parasitic capacitor 220 located within each cell 100, with one terminal connected to a word line and one terminal connected to floating gate 103 within the cell.
The effect of parasitic capacitors 210 is that there is voltage coupling between adjacent word lines and control gate lines that responds to changes in voltage on the word lines and/or control gate lines. The effect of parasitic capacitors 220 is that there is voltage coupling between word lines and floating gates within each cell 100 that responds to changes in voltage on the word lines and/or floating gates.
Parasitic capacitors 210 and 220 will cause word lines and control gate lines to take longer to charge to a certain voltage and longer to discharge. This parasitic capacitance has the unwanted effect of varying the current through each cell 100 during a discharge, which can cause read errors. As a result, the margin of error for read sensing operations is reduced. The problem is exacerbated as the target switching speed of the word line and control gate lines increases.
In addition, each word line and control gate line will have a large parasitic resistance. This resistance is due to the relative small size of the devices and the line width. The parasitic resistance can be modeled with parasitic resistors 230 located between cells 100 in each row.
FIG. 3 provides an example of the negative effect of this parasitic capacitance and parasitic resistance. In this example, word line 201 is selected for a read operation and is driven high. The voltage on control gate line 202 increases to VCG+ΔV from VCG due to coupling with word line 201, and then discharges down to VCG. After word line 201 discharges, control gate 202 discharges to VCG−ΔV and then charges back to VCG.
The additional ΔV on control gate line 202 causes an increase of cell current during the read operation. If the read operation does not provide sufficient time for control gate line 202 to discharge from VCG+ΔV to VCG, then a selected cell that is storing a “0” may be misinterpreted as containing a “1.” To avoid this problem, the switching speed must allow for a discharge period on the order of 10's of nanoseconds. Thus, parasitic capacitance and parasitic resistance will result in a less accurate system.
What is needed is a flash memory system that reduces the parasitic capacitance between word lines and control gate lines and between word lines and floating gates in a flash memory system.